1. Field of the Invention
The present invention relates to a memory circuit with a redundant configuration, and more particularly to a memory circuit where a drop in access speed due to redundancy judgment is prevented.
2. Description of the Related Art
A semiconductor memory device has a redundant configuration for repairing defective cells which are generated due to miniaturization as capacity increases and other causes. Various redundant configurations are used for such semiconductor memories as DRAM, SRAM, FeRAM and EEPROM (flash memory). Of these, flash memory uses a redundant configuration of bit lines as a repair method of defective cells. In other words, a bit line to which a defective cell belongs is replaced with a bit line in a redundant cell side for reading. This memory is stated in Japanese Patent Laid-Open No. 2000-231795 (published on Aug. 22, 2000).
In this kind of flash memory, defects of word lines and sectors, which are the units of erasing, are becoming a major cause of a drop in yield, due to increasing capacity. Therefore for a large capacity flash memory, a redundant configuration of word lines and a redundant configuration of sectors are being proposed. A flash memory has a plurality of sectors in a memory block. In such a configuration, a spare sector for repairing is provided in the memory block. And if the supplied address and the address of the defective sector (hereafter redundant address) match, the spare sector is selected instead of the regular sector.
A drop in access speed is the problem in such a memory with a redundant configuration. In other words, the address to be supplied and the redundant address are compared, and if they do not match, the data of the regular sector is read as is, but if they match, it is necessary to select the spare sector side and read the data. Therefore selection start timing at the spare sector side delays for the amount of time required for comparison judgment with the redundant address. In particular, when the word lines at the spare sector side are driven after judgment of the redundant address is completed, a drop in access speed is more conspicuous than the bit line redundant configuration.
Also along with disposing spare sectors for repairing defects, a spare sector operation test is required at pre-shipment testing. The spare sector can be accessed by writing the redundant address in the redundant memory, but it is desirable to perform an operation test of the spare sector before writing to the redundant memory. It is also necessary to perform an operation test of the repaired regular sector to verify defective mode after replacing with the spare sector by writing the redundant address. In such a case, even if the redundant address is written, an operation test of the replaced regular sector must be performed.